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Low Power Data In

IP.com Disclosure Number: IPCOM000085220D
Original Publication Date: 1976-Mar-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 2 page(s) / 35K

Publishing Venue

IBM

Related People

Park, SJ: AUTHOR

Abstract

Depicted in the drawing is a low-power data-in circuit for use in a monolithic memory array. The circuit includes a three-way OR circuit transistors T1, T2, T3), a pair of inverters (T4, T5), and a pair of emitter-followers (T6, T7).

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Low Power Data In

Depicted in the drawing is a low-power data-in circuit for use in a monolithic memory array. The circuit includes a three-way OR circuit transistors T1, T2, T3), a pair of inverters (T4, T5), and a pair of emitter-followers (T6, T7).

With a downlevel (write) signal impressed on the base of transistor T2, an input signal impressed on the terminal Vin results in the circuit providing a true and a complement output signal at output nodes Phi and Phi. With an uplevel (read) signal impressed on the base of T2, the signals on output nodes phi and phi are at a downlevel regardless of the input signal (up or down).

This circuit has low-power dissipation, since only one current source is used for the true-complement generation and read/write control function. In addition, the driver transistor is tied to the VR supply rather than VEE supply.

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