Browse Prior Art Database

Array Row Driver NPN Transistor

IP.com Disclosure Number: IPCOM000085221D
Original Publication Date: 1976-Mar-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 2 page(s) / 91K

Publishing Venue

IBM

Related People

Battista, MA: AUTHOR [+3]

Abstract

Described is a fast high-current NPN transistor designed compact enough to fit within the periodicity of memory array cells in a monolithic memory. The advantages include even current distribution to the collector, emitter and Schottky barrier diode (SBD) regions, in addition to, low collector series resistance, small area for high-density chip layouts, and special performance.

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Array Row Driver NPN Transistor

Described is a fast high-current NPN transistor designed compact enough to fit within the periodicity of memory array cells in a monolithic memory. The advantages include even current distribution to the collector, emitter and Schottky barrier diode (SBD) regions, in addition to, low collector series resistance, small area for high-density chip layouts, and special performance.

The topographic view of the silicon levels are shown in Fig. 1. The device uses a common subcollector bed with three separate base regions. Four collector contacts are used to decrease collector series resistance along with six collector-base SBD clamps. The SBD's are distributed along the device to accumulate enough area, thereby ensuring a low enough clamp voltage at high- current levels.

Fig. 2 shows the topographic view of the device contacts along with first and second level interconnection metal. The four collector contacts are connected directly through interlevel via holes to second-level metal, which distributes current to all memory cells in a given array row. Base and emitter contacts are arranged conveniently to minimize silicon area, allowing wiring at first-level metal to the driver circuitry, not shown.

A partial sectional view is shown in Fig. 3 which is typical of the device vertical cross section.

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