Browse Prior Art Database

Word Address True Complement Generator

IP.com Disclosure Number: IPCOM000085222D
Original Publication Date: 1976-Mar-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 2 page(s) / 37K

Publishing Venue

IBM

Related People

Holobinko, J: AUTHOR [+3]

Abstract

Depicted in the drawing is a circuit of a word address true-complement generator for use in a monolithic memory array. The input voltage swing (VIN) is normally from -1.0 to -2.0 volts. A current switch input is used with its complementary input tied to the VR supply. Schottky barrier diodes are used to prevent the input transistors 13C and 13D from saturating. The base resistors R1 are used to insure input net stability.

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Word Address True Complement Generator

Depicted in the drawing is a circuit of a word address true-complement generator for use in a monolithic memory array. The input voltage swing (VIN) is normally from -1.0 to -2.0 volts. A current switch input is used with its complementary input tied to the VR supply. Schottky barrier diodes are used to prevent the input transistors 13C and 13D from saturating. The base resistors R1 are used to insure input net stability.

The input current switch has one input transistor 13C or 13 D conducting, with the other complementary transistor totally off. Connected to the collectors of these two devices are identical resistors R2. The value of resistors R2 is chosen along with an appropriate constant-current source components, transistor 9E and resistor R3, to achieve appropriate performance and DC operating levels.

If the input (VIN) is high, the input transistor 13C is "on" and its complementary transistor 13D is "off". The collector (Node 2) of transistor 13C is low and its potential is defined by the current through the collector resistor R2. This voltage is also present on the base of the driver transistor 15A. Thus, the decode output (Node 3) is high, or "in phase" to the input VIN.

Concurrently, since the input transistor 13C is on, its complementary transistor 13D is off, with its collector high (Node 4). The base of the driver transistor 15B is high. Transistor 15B is thus forward biased and on. The decode output (Node 5) is...