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Lateral PNP Structure for Memory Cell

IP.com Disclosure Number: IPCOM000085223D
Original Publication Date: 1976-Mar-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 2 page(s) / 72K

Publishing Venue

IBM

Related People

Battista, MA: AUTHOR [+3]

Abstract

Described is a lateral PNP transistor structure for use in a memory cell array. A topographic view of the structure is shown in Fig. 1, and sectional view 2-2 is shown in Fig. 2.

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Lateral PNP Structure for Memory Cell

Described is a lateral PNP transistor structure for use in a memory cell array. A topographic view of the structure is shown in Fig. 1, and sectional view 2-2 is shown in Fig. 2.

The structure minimizes two inherent problems with this type of device. The first problem is that some of the emitter current, rather than being collected at the collector(s), is lost as a parasitic current to the isolation (see Fig. 1). This is especially significant if the emitter is close to isolation with no intervening collector. This problem is virtually eliminated with the structure of Fig. 1, since the collectors effectively surround the emitter.

The other problem with these devices in memory cell arrays, is one of maintaining uniform current distribution among the many devices connected to a common-current source. The emitters of many (72 as a typical example) devices are connected together with a second level of metallization. The bases of these devices are a common subcollector.

When the emitter currents are high, the base currents are also high (about 1/2 the value of emitter currents, because of current gains of about 1 in these devices). This would result in large voltage drops in the relatively high-resistivity subcollector, causing an unbalance of currents among the devices.

The described structure minimizes this problem by including contacts to the subcollector (base of the PNP's) every four cells along a row. The contacts are connec...