Browse Prior Art Database

Set Reset Shift Register Latch Using a Polarity Hold Shift Register Latch

IP.com Disclosure Number: IPCOM000085225D
Original Publication Date: 1976-Mar-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 2 page(s) / 43K

Publishing Venue

IBM

Related People

DasGupta, S: AUTHOR [+2]

Abstract

Reference is made to the drawing. Depicted therein is an efficient implementation of a set-reset shift register latch using a polarity-hold shift register latch. It requires only one additional AND-INVERT gate over what is required for the polarity-hold shift register latch. As illustrated in the drawing, the same implementation may be used for a reset dominant or set dominant latch depending on the function that g1 and g2 serve.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 100% of the total text.

Page 1 of 2

Set Reset Shift Register Latch Using a Polarity Hold Shift Register Latch

Reference is made to the drawing. Depicted therein is an efficient implementation of a set-reset shift register latch using a polarity-hold shift register latch. It requires only one additional AND-INVERT gate over what is required for the polarity-hold shift register latch. As illustrated in the drawing, the same implementation may be used for a reset dominant or set dominant latch depending on the function that g1 and g2 serve.

Reference is made to U. S. Patent No. 3,783,254, granted to Edward B. Eichelberger and entitled "Level Sensitive Logic System".

1

Page 2 of 2

2

[This page contains 3 pictures or other non-text objects]