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Regenerative TTL Receiver Using Enhancement and Depletion FET Devices

IP.com Disclosure Number: IPCOM000085226D
Original Publication Date: 1976-Mar-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 3 page(s) / 31K

Publishing Venue

IBM

Related People

Elliott, JC: AUTHOR [+2]

Abstract

Transistor T1 is biased by +V. Transistor T1 is always conducting. TTL voltage levels are applied to the input node VIN. Transistor T2 functions as a source-follower. The gate of T2 is biased by the feedback voltage from the output node Vout. Transistors are depletion load devices. +V >/- MPUL of VIN, where MPUL is the most-positive uplevel.

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Regenerative TTL Receiver Using Enhancement and Depletion FET Devices

Transistor T1 is biased by +V. Transistor T1 is always conducting. TTL voltage levels are applied to the input node VIN. Transistor T2 functions as a source-follower. The gate of T2 is biased by the feedback voltage from the output node Vout. Transistors are depletion load devices. +V >/- MPUL of VIN, where MPUL is the most-positive uplevel.

When the input signal applied at input node VIN is at or below MPDL (most- positive downlevel), the gate of transistor T5 is slightly more positive and T5 is off. Transistor T4 presents a low-resistance path to charge the output node Vout to approximately +V. The +V potential at the output node Vout is applied to the gate of transistor T2 via the feedback path shown. This biases T2 in its low- resistance triode region. Both T1 and T2 are operating in their low-resistance regions. Transistor T2 is a larger device than T1 and presents a lower resistance path when "on". The effect of T1 in parallel with T2 on produces a low-resistance path and good noise margins for keeping transistor T5 off.

When the potential applied to input node VIN is switched positive, to or above LPUL (least-positive uplevel), this potential is applied through the low-resistance path provided by transistor T1 in parallel with T2 to the gate of T5 and drain of T3. Because of the voltage divider effect between T3 in parallel with T1 and T2, the gate of T5 is slightly more positive than the potential impressed on input node VIN.

Three things occur which result in the gate of transistor T5 being driven more positive than the potential on input node VIN and insuring that T5 is turned fully on. First, the gate-to-source voltage of T1 and T2 has dropped and their resistance has increased, which coupled with the voltage divider effect with T3, drives the gate of T5 more positive. Second...