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Testing Programmable Logic Arrays on Cards

IP.com Disclosure Number: IPCOM000085237D
Original Publication Date: 1976-Mar-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 2 page(s) / 32K

Publishing Venue

IBM

Related People

Bono, RC: AUTHOR [+2]

Abstract

When testing multiple components on a card, it is advantageous at times to be able to isolate components and test them separately to be able to locate faults. A method for doing this with programmable logic arrays is described below.

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Testing Programmable Logic Arrays on Cards

When testing multiple components on a card, it is advantageous at times to be able to isolate components and test them separately to be able to locate faults. A method for doing this with programmable logic arrays is described below.

Programmable logic arrays can have internal feedbacks, external inputs and outputs. When an external output 01 is fed back to an external input I1, testing may be difficult due to the following. If 01 is at ground potential (0 volts) and it is desirable to have I1 at a positive level, it is impossible to raise the voltage or potential via an external signal on I1. It may also take a large number of sequential patterns on the inputs to cause 01 to go a positive potential. Note that if 01 is at a positive potential Test Point 1 can be grounded or left alone, thus causing a logical 1 or 0 to be placed on I1 as desired.

The method described states that if an illegal input combination exists, this combination with the use of one word line causes all external outputs to go to a positive level. This substantially reduces the number of input sequences to achieve this. This can also result in module-to-module isolation.

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