Browse Prior Art Database

Memory Cell Structure

IP.com Disclosure Number: IPCOM000085240D
Original Publication Date: 1976-Mar-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 2 page(s) / 42K

Publishing Venue

IBM

Related People

Abbas, SA: AUTHOR [+2]

Abstract

The present method for making a one-device memory cell increases capacitance, Cj, while avoiding any adverse effects. The substrate doping under the storage node diffusion is increased. The process sequence for a silicon gate device is as follows:. Crow thick thermal oxide on (100) p-doped silicon substrate; 2 ohm-cm. Define device area by etching the thick oxide. Grow the gate oxide, for example 500 Angstroms, and chemically vapor deposit intrinsic polysilicon film thereover. The polysilicon layer is then etched to form the self-aligning gate which is later doped during the source and drain diffusion. Then: (1) Diffuse or ion implant the n+ source and drain. (2) Drive in the N+ impurity in nonoxidizing ambient. (3) Block out bit/sense (B/S) diffusion with photoresist.

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Memory Cell Structure

The present method for making a one-device memory cell increases capacitance, Cj, while avoiding any adverse effects. The substrate doping under the storage node diffusion is increased. The process sequence for a silicon gate device is as follows:. Crow thick thermal oxide on (100) p-doped silicon substrate;

2 ohm-cm. Define device area by etching the thick oxide.

Grow the gate oxide, for example 500 Angstroms, and chemically

vapor deposit intrinsic polysilicon film thereover. The

polysilicon layer is then etched to form the self-aligning

gate which is later doped during the source and drain diffusion. Then:
(1) Diffuse or ion implant the n+ source and drain.
(2) Drive in the N+ impurity in nonoxidizing ambient.
(3) Block out bit/sense (B/S) diffusion with photoresist.
(4) Ion implant boron into storage node region to form Fig. 2

structure. And:
(5) Implant anneal.

The process is then continued to form the usual metal contacts, connections between devices, passivation, and chip input-output connections.

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