Browse Prior Art Database

MOSFET Memory Cell Using Junction Capacitance

IP.com Disclosure Number: IPCOM000085247D
Original Publication Date: 1976-Mar-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 2 page(s) / 58K

Publishing Venue

IBM

Related People

Abbas, SA: AUTHOR

Abstract

A cross section of a metal-oxide semiconductor field-effect transistor (MOSFET) one-device memory cell is shown in the figure. Effectively it is a bipolar-type structure with a subcollector N+ diffused in the substrate with an epitaxial layer grown thereover. The epitaxial layer could either be P-type or N-type as grown and doped later by ion implantation or a P diffusion. There is an N+ reach-through diffusion to connect the N+ subcollector. An emitter-like N+ diffusion forms the source or the drain of the FET.

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MOSFET Memory Cell Using Junction Capacitance

A cross section of a metal-oxide semiconductor field-effect transistor (MOSFET) one-device memory cell is shown in the figure. Effectively it is a bipolar-type structure with a subcollector N+ diffused in the substrate with an epitaxial layer grown thereover. The epitaxial layer could either be P-type or N-type as grown and doped later by ion implantation or a P diffusion. There is an N+ reach-through diffusion to connect the N+ subcollector. An emitter-like N+ diffusion forms the source or the drain of the FET.

The storage node is under the device itself rather than to the side. This results in an efficient utilization of area. There is enough capacitance to make the operation of the array feasible.

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