Browse Prior Art Database

Split Field Alignment Marks

IP.com Disclosure Number: IPCOM000085252D
Original Publication Date: 1976-Mar-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 2 page(s) / 53K

Publishing Venue

IBM

Related People

Dolan, GF: AUTHOR [+2]

Abstract

The split vernier alignment marks shown in Fig. 1 affords a 1X alignment technique for semiconductor wafers that reduces skew and magnification errors, as compared to standard 1X alignment techniques. They also improve the operator's ability to judge alignment, hence reducing the operator alignment tolerance. Similar verniers illustrated in Fig. 2 are used for stepping marks for direct readout of estimated skew, magnification and stepping errors.

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Split Field Alignment Marks

The split vernier alignment marks shown in Fig. 1 affords a 1X alignment technique for semiconductor wafers that reduces skew and magnification errors, as compared to standard 1X alignment techniques. They also improve the operator's ability to judge alignment, hence reducing the operator alignment tolerance. Similar verniers illustrated in Fig. 2 are used for stepping marks for direct readout of estimated skew, magnification and stepping errors.

An important advantage of the alignment marks is that they are used in the kerf areas of each chip rather than within the active chip area. Yet, they yield center-of-chip alignment by placement on or near the Y - Y chip axis, with compensation of skew by the vertical marks, compensation of magnification errors by the horizontal marks, and compensation of other overlay errors by use of vertical and horizontal marks.

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