Browse Prior Art Database

Half Wired Multiplier

IP.com Disclosure Number: IPCOM000085255D
Original Publication Date: 1976-Mar-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 2 page(s) / 35K

Publishing Venue

IBM

Related People

Dauby, A: AUTHOR [+2]

Abstract

The ALU of most microprocessors is not provided with a wired multiplicator. Consequently, the number of instructions to be run to generate a multiplication is quite high. This required number of instructions may be reduced by specializing two registers of the microprocessor.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 68% of the total text.

Page 1 of 2

Half Wired Multiplier

The ALU of most microprocessors is not provided with a wired multiplicator. Consequently, the number of instructions to be run to generate a multiplication is quite high. This required number of instructions may be reduced by specializing two registers of the microprocessor.

Suppose that the microprocessor is provided with two stacks of registers SA and SB feeding the ALU. In order to simplify this description, assume that the multiplicand A to be processed is a positive number binary encoded with eight bits, while the multiplier B is a signed 2's complement sixteen-bit word. In the event A is negative, A and B would be replaced by their inverse.

These operands are stored in registers belonging to SA and SB, respectively. In addition, two registers (X and Y) are specialized as shown in Fig. 2. X is an eight-bit buffer register and Y an eight-bit shift register. A write XX0 instruction enables loading both registers X and Y, while an unloading operation is controlled with read instructions READ XX0 or READ XX1, respectively.

The multiplication operation is performed by using the well-known add and shift method. The multiplier B is tested one bit at a time and depending on whether this bit is 0 or 1, either a 0 is added to the product partial result and shifted one bit position to the right, or A is added to it. These operations are performed here by feeding the lowest order bit of the partial product to register Y, while feeding the other bit...