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Noninverting Logic Using Depletion Load

IP.com Disclosure Number: IPCOM000085264D
Original Publication Date: 1976-Mar-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 2 page(s) / 25K

Publishing Venue

IBM

Related People

Cukier, M: AUTHOR

Abstract

Depletion load field-effect transistor (FET) circuits can help in implementing a logic based on OR and AND gates with a logic level rising up to VCC and by requiring fewer transistors than enhancement technology.

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Noninverting Logic Using Depletion Load

Depletion load field-effect transistor (FET) circuits can help in implementing a logic based on OR and AND gates with a logic level rising up to VCC and by requiring fewer transistors than enhancement technology.

The basic circuit used here is made of a FET of the depletion mode type connected as a source load circuit to an enhancement mode FET used as active element. The output voltage is therefore in phase with the input voltage applied to the gate of the active transistor. By doing so, several interesting logic combinations may be implemented.

As shown, for instance, in the figure, such basic circuits may be combined to provide a multiple output gate. A series of active devices T1, T2, T3, T4 are connected in cascade with the T1 drain connected to a power supply VDD. Depletion loads L1, L2, and L3 are connected to transistors T2, T3, and T4. By applying logic levels A, B, C, D on the T1-T4 gates, the out combinations A.B, A.B.C. and A.B.C.D are obtained. The outputs occur simultaneously.

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