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Microprogrammed Digital Filter

IP.com Disclosure Number: IPCOM000085265D
Original Publication Date: 1976-Mar-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 3 page(s) / 39K

Publishing Venue

IBM

Related People

Esteban, D: AUTHOR [+3]

Abstract

A digital filter computes each sample Y(i) of the filtered output signal by accumulating a series of input samples X(i-n), each weighted by a coefficient C(n). (Image Omitted)

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Microprogrammed Digital Filter

A digital filter computes each sample Y(i) of the filtered output signal by accumulating a series of input samples X(i-n), each weighted by a coefficient C(n).

(Image Omitted)

Implementation of the filter is simplified by using integral values for the coefficients. In addition, by properly coding the coefficients. an additional gain in computing power may be obtained. Here both positive and negative bit values are used to minimize the number of bits 1 for each coefficient. Assuming a filter with coefficients 1, 3, 10, -3, -1, they will be coded, respectively: C(o) = 1 = 0 0 0 1

C(1) = 3 = 0 1 0 -1

C(2) = 10 = 1 0 1 0

C(3) = -3 = 0 -1 0 1

C(4) = -1 = 0 0 0 -1

Reading of the coefficients per row of the same weight permits the substitution of addition/subtraction and shift operations for conventional multiplication operations.

These three features are incorporated in the microprogrammed implementation of a digital filter, shown on the figure.

The input samples are written into Sample Memory through an IN gate controlled by a Strobe In signal. The coefficients are stored in a programmable read-only memory (PROM) in the form of microcode instructions. A microcode instruction provides the address of the sample to be processed and controls the addition/subtraction and shift operations.

The sample read from the Sample Memory is applied to an input of an adder. The output from the adder is loaded into a shift/accumulator (S/A) register in which shift operations take place selectively. The contents of shift/accumulator register is applied to the output of the filter through an OUT Gate and to the other input of the adder.

Listed below is the set of microcode instructions which controls the sequence of operations, assuming a 5-coefficient filter with the above-recited coefficient values. INSTRUCTION DESCRIPTION

Data Shift Add/subt.

Address

Nr.1 0 0 0 0 1 - Read sample from address 0, add with S/A register

contents, result in S/A

register, no shift.

Nr.2 0 0 1 0 0 - Read sample from address 1, subtract from S/A register

1

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contents, result in S/A

register, no shift.

Nr.3 0 1 1 0 1 - Read sample from address 3, add with S/A register

contents, result in S/A

register, no shift.

Nr.4 1 0 0 1 0 - Read sample from address 4, subtract from S/A register

contents, result in S/A

register, shift S/A register

contents one bit position to

the right.

Nr.5 0 1 0 1 1 - Read sample from addres...