Browse Prior Art Database

Address Translation Bypass

IP.com Disclosure Number: IPCOM000085302D
Original Publication Date: 1976-Mar-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 3 page(s) / 44K

Publishing Venue

IBM

Related People

Heald, AT: AUTHOR

Abstract

This method may allow a computer system to improve its performance by reducing the overhead involved when running in address translation mode. This overhead reduction can be achieved by those operating systems that use an area of storage in which virtual addresses are equal to real addresses. This virtual equal real area normally is at the lowest address part of storage, which includes all of the operating system nucleus plus some fixed storage. When a problem program calls on a control program function within the virtual equal real area, the normal translation process is used in current systems even though the input or virtual address will equal the output or real address.

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Address Translation Bypass

This method may allow a computer system to improve its performance by reducing the overhead involved when running in address translation mode. This overhead reduction can be achieved by those operating systems that use an area of storage in which virtual addresses are equal to real addresses. This virtual equal real area normally is at the lowest address part of storage, which includes all of the operating system nucleus plus some fixed storage. When a problem program calls on a control program function within the virtual equal real area, the normal translation process is used in current systems even though the input or virtual address will equal the output or real address.

A way of eliminating the translation overhead, is to run in real or nontranslation mode when within the virtual equal real area of the system. The problem with this is that the operating system will not have addressability to the virtual equal virtual area of the system. The performance improvement realized by not having to reference translation tables in real storage is offset by the performance degradation of switching modes, and of loading real addresses when referencing storage within the virtual equal virtual area.

This leaves a trade off, the convenience of running in translation mode in contrast to the better performance of running in real mode. A technique that combines the advantages of both methods would have the operating system load a system control register, which will be referred to as the Virtual=Real control register, with the highest continuous virtual equal real address starting from location zero. During any subsequent translation activity, the machine would compare the virtual address with the address within the Virtual=Real control register. If the virtual address is low or equal, than the virtual address is used as the real address. If the virtual address is high then the normal translation process is used.

The accompanying figure illustrates how the Virtual=Real address translation bypass may be implemented. The following paragraph numbers correspond to the circled number in the figure.
(1) The operating system loads the Virtual=Real control register

with the highest continuous virtual equal real address

starting from location zero.
(2) The translation process in the machine compares any virtual

address generated with the address in the Virtual=Real

control register.
(3) If the virtual address is equal or lower than the address in

the Virtual=Real control register, the tra...