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Display Refresh Mechanism Employing a Multisegmented Buffer

IP.com Disclosure Number: IPCOM000085312D
Original Publication Date: 1976-Mar-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 4 page(s) / 78K

Publishing Venue

IBM

Related People

Cummins, DA: AUTHOR [+2]

Abstract

A multisegmented display is shown in Fig. 1. It is comprised of a header message, such as the titles of the documents being displayed, one or more text areas, and a system message area. Independent operations may be performed on the text data, such as insert or delete data and particularly the operation of scrolling each text area without affecting the other text or the message areas. Also, the size of each text area may be varied as well as the orientation of the text separation; i.e., horizontal or vertical.

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Display Refresh Mechanism Employing a Multisegmented Buffer

A multisegmented display is shown in Fig. 1. It is comprised of a header message, such as the titles of the documents being displayed, one or more text areas, and a system message area. Independent operations may be performed on the text data, such as insert or delete data and particularly the operation of scrolling each text area without affecting the other text or the message areas.

Also, the size of each text area may be varied as well as the orientation of the text separation; i.e., horizontal or vertical.

A means of realizing these functions is shown in Fig. 2. A central processing unit (CPU) has access to the entire library of display data text and, under external commands, selects a portion to be displayed. This data is placed into the display buffer, whereupon it is used to cause a character pattern to be displayed upon the cathode-ray tube (CRT).

The address controls allow the organization of the display buffer to be independent of the display arrangement as shown in Fig. 3. The only restrictions are that message and text data be contiguous for each area and that a fixed reserved section of the buffer be allocated for the starting address of each area.

The data flow is shown in Fig. 4. The operation is such that coded data placed into the display buffer 5 is retrieved sequentially as the deflection and sync controls cause the electron beam to scan the CRT. Data from the buffer 5 is passed through the dot pattern generator, in order to translate the coded data into a series of dots that form the displayed character. The display buffer 5 is a random access memory and, as such, the CPU can place data into the buffer by providing an address and the display data to be stored.

The display operation begins when the deflection and sync controls cause the electron beam to move to the top of the screen during vertical retrace. During this time the gating and buffer cycle controls cause the pointer counter 2 to reset to zero. This pointer value is then passed through gates 3 and into counter 4. This forms an address to the display buffer 5 which will contain the starting address of the header display area. The starting address is a pointer to the location of the header display data in the buffer. This address is retrieved from the buffer 5 and placed into the Text 1 register 6. Text register 6 now contains the buffer address of the first character to be displayed in the header message.

When the electron beam is ready to paint the first scan of the header message, the contents of the Text 1 register 6 are passed into counter 4 and are used to access the first character of the header message. This coded character is read from the buffer 5 and passed through the dot pattern generator to be painted on the CRT screen. The counter 4 is incremented by 1 in order to address the second character of the header message, which is then read and passed through the dot pattern generator t...