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First Order Phase Locked Loop Data Filter

IP.com Disclosure Number: IPCOM000085340D
Original Publication Date: 1976-Mar-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 3 page(s) / 28K

Publishing Venue

IBM

Related People

Elliott, WY: AUTHOR

Abstract

Bessel or linear-phase filters can only approximate linear phase over a given bandwidth. Accordingly, practical designs cause some intersymbol distortion and, in addition, are complex and difficult to fabricate. The first order phase-locked loop filter described, effectively filters high-frequency noise, particularly, at low signal-to-noise ratios, while maintaining intersymbol integrity.

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First Order Phase Locked Loop Data Filter

Bessel or linear-phase filters can only approximate linear phase over a given bandwidth. Accordingly, practical designs cause some intersymbol distortion and, in addition, are complex and difficult to fabricate. The first order phase- locked loop filter described, effectively filters high-frequency noise, particularly, at low signal-to-noise ratios, while maintaining intersymbol integrity.

As shown in the figure, the filter comprises a hard limiter 10, a multiplier 12, a level shifter 14 and a voltage-controlled oscillator 16. The filter can be implemented using analog circuits to perform the functions shown, or it can be implemented using digital circuits. In the latter case, the function of hard limiter 10 can be performed by a comparator having a logic output, and the phase detection function can be performed by an exclusive OR circuit. Voltage- controlled oscillator 16 is designed so that when its input is a logical "0", it does not oscillate (zero frequency), and when its input is a logical "1" it runs at twice the bit rate of the input signal.

The feature that makes the described circuit configuration unique, and useful as a data filter, is the concept of driving voltage-controlled oscillator 16 from zero frequency to twice the free-running frequency F(O). This enables the system to follow the input data and produce a delayed and filtered replica thereof.

Referring to the figure, the voltage at the input to the filter, not shown, is a binary signal such that all values more positive than some reference level represent logical 1's and all values more negative than the reference level represent logic 0's. Therefore, the output of hard limiter 10 is a binary voltage (in this case +1 and -1 v...