Browse Prior Art Database

Solder Bonding of Silicon Chips with Through Holes

IP.com Disclosure Number: IPCOM000085359D
Original Publication Date: 1976-Mar-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 2 page(s) / 50K

Publishing Venue

IBM

Related People

Kuhn, L: AUTHOR [+2]

Abstract

This is a solder bond packaging technique for silicon substrates containing through-holes. Such a package is required for silicon charge electrode arrays in ink jet printing systems and multiple-chip (wafer) stacked packages in large-scale integration (LSI). It was found that solder balls may be formed on pads on a silicon substrate without allowing the solder to wet the through-holes.

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Solder Bonding of Silicon Chips with Through Holes

This is a solder bond packaging technique for silicon substrates containing through-holes. Such a package is required for silicon charge electrode arrays in ink jet printing systems and multiple-chip (wafer) stacked packages in large-scale integration (LSI). It was found that solder balls may be formed on pads on a silicon substrate without allowing the solder to wet the through-holes.

In Fig. 1, an N-type silicon substrate 2 including a through-hole or slot 3 is coated with a silicon oxide layer 4 and has a P-doped region 6, and a thin metal film 8 formed in a window in the oxide layer 4. The substrate 2 is immersed in acid flux and dipped into a low-temperature solder bath, and solder adheres to the metal film 8 resulting in a solder ball 10 being formed on the silicon substrate
2.

In Fig. 2 the substrate 2 is illustrated and is bonded to substrates 12 and 14 by way of low-temperature solder reflow techniques, resulting in the substrate 2 being bonded to the substrate 12 by solder balls 10. The substrate 2 is bonded to the substrate 14 by the same solder reflow by a solder ball 16, which is formed on the substrate 14 in a manner similar to that utilized in forming the solder ball 10 on the substrate 2.

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