Browse Prior Art Database

Exclusive OR Gate in Latching Josephson Tunneling Logic

IP.com Disclosure Number: IPCOM000085386D
Original Publication Date: 1976-Mar-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 2 page(s) / 30K

Publishing Venue

IBM

Related People

Anacker, W: AUTHOR

Abstract

Fig. 1 depicts the schematic of a 4-gate Josephson tunneling "exclusive OR" gate, which can be used to perform the "exclusive OR" and the "inverted exclusive OR" function. The truth table for the exclusive OR function is shown in Fig. 2a and that for the inverted exclusive OR function in Fig. 2b. Fig. 3 indicates how the inputs a to d of the circuit of Fig. 1 are to be connected to the true (X1,X2) and complement (X1,X2) values to perform the proper function.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 100% of the total text.

Page 1 of 2

Exclusive OR Gate in Latching Josephson Tunneling Logic

Fig. 1 depicts the schematic of a 4-gate Josephson tunneling "exclusive OR" gate, which can be used to perform the "exclusive OR" and the "inverted exclusive OR" function. The truth table for the exclusive OR function is shown in Fig. 2a and that for the inverted exclusive OR function in Fig. 2b. Fig. 3 indicates how the inputs a to d of the circuit of Fig. 1 are to be connected to the true (X1,X2) and complement (X1,X2) values to perform the proper function.

1

Page 2 of 2

2

[This page contains 2 pictures or other non-text objects]