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"Creepy" Counter Scheme

IP.com Disclosure Number: IPCOM000085401D
Original Publication Date: 1976-Apr-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 2 page(s) / 53K

Publishing Venue

IBM

Related People

Saenz, G: AUTHOR

Abstract

The circuit of Fig. 1 is a divide-by-eight "creepy" counter. The counter uses a shifting technique in four bits to generate pulses which can be combined through logic gates to produce noise-free clock pulses, because only one of the S-R latches changes state each clock cycle.

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"Creepy" Counter Scheme

The circuit of Fig. 1 is a divide-by-eight "creepy" counter. The counter uses a shifting technique in four bits to generate pulses which can be combined through logic gates to produce noise-free clock pulses, because only one of the S-R latches changes state each clock cycle.

Since a four-bit counter is used, there are sixteen possible states. Only eight states are used in the valid count sequence. Therefore, eight counter states are invalid. The operation of the circuit is such that during a power-on-reset (POR) cycle, the state of the circuit does not require a reset. The initial state may define either a valid counter state or an invalid counter state. The next state following any invalid counter state is a valid state. The circuit requires, at most, two clock cycles to enter a valid counting sequence, which is usually considerably less time than that required for a machine POR cycle.

S-R latches A and C are clocked by clock pulses TA from nonoverlapping clock generator 5. S-R latches B and D are clocked by pulses TB from generator
5. Pulses TA and TB do not overlap. In both the valid counter states and invalid counter states tables of Fig. 2, the columns CD define a particular counter state while the columns TA and TB define the next counter state dependent upon whether the TA or the TB pulse is the next clock pulse.

Assume that the output of latches A-D define an invalid state upon initial application of power to these latches and to...