Browse Prior Art Database

Microprogram Cycle Control

IP.com Disclosure Number: IPCOM000085406D
Original Publication Date: 1976-Apr-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 3 page(s) / 42K

Publishing Venue

IBM

Related People

Tutt, WE: AUTHOR

Abstract

Cycle controller 100 reduces the size of read-only storage (ROS) unit 101 required for microprogramming a data processor.

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Microprogram Cycle Control

Cycle controller 100 reduces the size of read-only storage (ROS) unit 101 required for microprogramming a data processor.

Output register 102 and control register 103 are loaded with ROS data bits in a conventional sequence, such that the outputs of register 103 remain valid while data from the next microcycle are being read into register 102. Output bits 105 control the data flow in the microprogrammed machine, not shown, while bits 106 are used to generate a partial address for the next microcycle, also in conventional fashion.

Normally, all operation-code bits 107 would be presented to ROS 101 simultaneously as a starting address for each machine instruction. To reduce the number of required ROS addresses, these bits are divided into two groups. Basic op-code bits 107A are gated to ROS address lines 108 through AND 109 and OR 110 by inverter 111 when "select" ROS output bit 112 is 0. When the basic operation code is to be varied, a 1 value of bit 112 gates modifier op-code bits 107B through AND 113 and OR 110 to the same address lines 108.

Since bit 112 is itself used to address ROS 101, the op-code modifier always uses a different ROS space than that containing the basic op-code words. In a system having four basic bits 107A and four modifier bits 107B, for example, this technique may reduce the size of ROS 101 by a factor of up to eight. The technique may be extended to include further op-code bit groups and select bits.

A second method for reducing the size of ROS 101 employs a "phase" ROS output bit 114 for inhibiting both of the AND gates 109 and 113, so that all of the address bits 108 are 0. Most data processors perform each instruction in two distinct phases. An instruction (I) phase fetches the instruction in the same way, regardless of its operation code, while an execution (E) phase executes different instructions differently, in accordance with their various operation codes.

If the ROS words for the I...