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Browse Prior Art Database

Digital Counter Control

IP.com Disclosure Number: IPCOM000085421D
Original Publication Date: 1976-Apr-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 2 page(s) / 54K

Publishing Venue

IBM

Related People

Winters, HO: AUTHOR

Abstract

One circuit controls the measurement by a digital counter of the frequency of occurrence of input pulses, or the duration of individual positive or negative pulses, over a wide range of timing values.

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Digital Counter Control

One circuit controls the measurement by a digital counter of the frequency of occurrence of input pulses, or the duration of individual positive or negative pulses, over a wide range of timing values.

Pulses occurring at an unknown frequency at input 1 are accumulated in a counter, for an interval between the resetting of the counter to zero and the gating of the counter contents into a register. A digital display connected to the register will then show the number of pulses occurring during the interval. For example, an interval of one second will give a display directly in hertz. The duration of single pulses at input 8 is displayed by stepping the counter at a known rate only while the pulse occurs. Thus, for example, a 1 MHz stepping rate will give a display readable directly in microseconds.

Timing is controlled by selecting (in B:CD code) timing pulses at any one of eight frequencies available from a decimal divider. Frequency measurement is selected by placing switch S1 in position A and duration measurement by placing it in position B. In the case of frequency measurement, flip-flop FFA is set to the Q state by the positive leading edge of the first timing pulse on line 2 which then enables an AND circuit &A to pass the input pulses to the stepping input +1 of the counter.

The positive edge of the second timing pulse steps FFA to Q state. The flip- flop FFA Q output initiates a display gate and hold-off signal via an exclusive OR c...