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Threshold Compensated FET Latch Circuit

IP.com Disclosure Number: IPCOM000085432D
Original Publication Date: 1976-Apr-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 2 page(s) / 30K

Publishing Venue

IBM

Related People

Rock, JE: AUTHOR

Abstract

This field-effect transistor (FET) circuit provides compensation for low-threshold devices used in a latch circuit as part of a timing chain driver.

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Threshold Compensated FET Latch Circuit

This field-effect transistor (FET) circuit provides compensation for low- threshold devices used in a latch circuit as part of a timing chain driver.

The trip point of a conventional grounded source cross-coupled latch circuit is determined when the gate-to-source (Vgs) of the off-device reaches the device threshold voltage Vth. When a latch is used to hold the output of a driver down, the hold-down device must be large to insure that the output does not rise above a threshold until the proper time. For low-threshold devices this requires an extremely large hold-down device.

When the current through the hold-down device is large and parasitic resistances are considered, it becomes extremely difficult to properly design the circuit. This circuit modification, implemented through simple layout techniques, allows the trip point of a latch to be raised.

The figure shows a typical delay stage circuit for a timing chain driver. The gates of transistors T3A and T3B are precharged to VC by a precharge pulse PC to transistor T6. The START pulse turns on transistors T2 and T5. Transistor T3A is designed to hold the output Vout down until T5 has discharged the parasitic capacitance of T3A sufficiently to cause the latch to change state, that is, to cause transistor T4 to turn on.

Assuming that device T3B and resistor R are not present and that device thresholds are low (Vth about 0.5 volt), 10 ma is being sunk by transistor T3A and 50...