Browse Prior Art Database

Address Buffer True Complement Generator

IP.com Disclosure Number: IPCOM000085434D
Original Publication Date: 1976-Apr-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 2 page(s) / 32K

Publishing Venue

IBM

Related People

Furman, A: AUTHOR

Abstract

This memory storage address inverter buffer is sensitive to low-level bipolar input voltages which are less than full field-effect transistor (FET) logic levels. The circuit provides full FET logic output levels for the true and complement of a single bipolar logic input signal, without using DC power and with minimum input loading.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 64% of the total text.

Page 1 of 2

Address Buffer True Complement Generator

This memory storage address inverter buffer is sensitive to low-level bipolar input voltages which are less than full field-effect transistor (FET) logic levels. The circuit provides full FET logic output levels for the true and complement of a single bipolar logic input signal, without using DC power and with minimum input loading.

In operation, during standby, when CS and DCS are low, restore pulse R turns on transistors T1 and T2 allowing bootstrap nodes N1 and N2 on the gates of output drivers T3 and T4 to charge to VH less one threshold VH-Vth, for example. Isolation devices T5 and T6 have their gates biased at a reference potential Vref causing node N3, on the gate of transistor T7, to charge toward Vref-Vth and node N4 to charge toward Vref-2Vth, assuming input SAR IN is low. If SAR IN, applied to the gate of transistor T8, is high node N4 may charge to a maximum of Vref-Vth depending on the potential of SAR IN.

In order to guarantee proper operation, such that node N3 remains charged when SAR IN is low and is fully discharged when SAR IN is high, SAR IN must be greater than the drain potential of transistor T8 when in the high state. This requirement is necessary in order to insure that node N3 will discharge quickly if SAR IN is high, without allowing transistor T7 to discharge node N2 through transistor T6 when CS goes high. The application of Vref to the gates of transistors T5 and T6 allows the drain potential...