Memory Sense Amplifier
Original Publication Date: 1976-Apr-01
Included in the Prior Art Database: 2005-Mar-02
This sense amplifier circuit provides improved operation and sensitivity for charge-transfer sensing, as described in U.S. Patent 3,764,906 by L. G. Heller, for the single field-effect transistor (FET)/capacitor memory cell described in U. S. Patent 3,811,076 by W. M. Smith, Jr. Improvement is achieved in view of the following improvements:
Memory Sense Amplifier
This sense amplifier circuit provides improved operation and sensitivity for
charge-transfer sensing, as described in U.S. Patent 3,764,906 by L. G. Heller,
for the single field-effect transistor (FET)/capacitor memory cell described in U.
S. Patent 3,811,076 by W. M. Smith, Jr. Improvement is achieved in view of the following improvements:
1. A DC level is maintained on the gate of the sense device. A read operation can be performed at any time after the bit lines are charged up without pulsing the gate of the sense/restore device.
2. An isolation device and capacitor are provided so that the voltage at the sense device gate is free from supply noise. This is necessary in order to maintain active operation. The gate capacitor is tied to the substrate and field shield the same as the bit line. The isolation device, only turned on at a stable time in the cycle, supplies charge lost through leakage. Because gate set (G.S.) is shut off before the bit lines are fully charged, small drops in VH (and VHA) will not shut off the sense device.
3. Dynamic range is increased in the low-threshold case. This is done with a compensating network that adjusts the gate voltage of the sense device, so that its source (bit line) recovers to a constant voltage in all cases (voltage; threshold) to about what it would have with VH on the gate, when VH is at the design minimum and thresholds are at their maximum.
Circuit Description: The figure is a schematic circuit of the sense amplifier, which uses a modification of the charge-transfer technique which maintains a constant voltage (VHA) on the gate of transistor T4, the sense device.
In standby, the voltage storage at node C is either LVHA (VHA - Vt of transistor T4) or at ground. The word line is at ground; the bit line is restored to LVHA by T4. The drain of transistor T4 (node A) is restored to VH by transistor T2 whose gate DHR is bootstrapped more than a threshold above VH. The latch node is externally held at VH so that transistors T5 and T6 are both off.
DHR remains high into a select cycle, thus continuing to restore the bit lines until immediately before the word line is selected. Then with DHR down and the word line up, storage capacitor CS pulls a charge Q (LVHA X Cs) out of the bit line if a low level was stored. Although the bit line moves a very small amount because of bit line capacitance C2, transistor T4 restores it to the original value with charge from the smaller capacitance C1 and a large voltage difference occurs at node A. If a high level is stored in C5, no charge is transferred and neither the bi...