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Circuit Supporting Structure With Antiringing Characteristics

IP.com Disclosure Number: IPCOM000085452D
Original Publication Date: 1976-Apr-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 2 page(s) / 64K

Publishing Venue

IBM

Related People

Ecker, ME: AUTHOR [+3]

Abstract

Chip-to-chip logic circuit communication nets consist of printed wires on modules, cards, and boards, as well as cables. When such nets are driven by high-speed drivers ringing can occur under certain conditions.

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Circuit Supporting Structure With Antiringing Characteristics

Chip-to-chip logic circuit communication nets consist of printed wires on modules, cards, and boards, as well as cables. When such nets are driven by high-speed drivers ringing can occur under certain conditions.

The ringing is unacceptable because of the danger of false switching and reduced noise margins.

Three basic methods are available for suppressing the ringing:

(a) Reduce switching speed of the driver(s).

(b) Restrict net configurations to those which are

immune from ringing.

(c) Use dampers on the net.

Method (a) is difficult to implement in high-speed technologies and it also defeats the purpose by slowing down the technology.

Method (b) becomes too restrictive to be practical.

Method (c) is a practical approach. Reference is made to Figs. 1 and 2 of the drawing.

In order to effect the damping circuits, a suitable copper pad B is placed directly over a transverse power distribution element V2 to form a parallel-plate capacitor. By any well-known technique, a resistive material A is deposited over and connected to the signal line S and the capacitor plate B. By suitable definitions of the geometries for material A and plate B, resistors are AC grounded via the capacitors as shown.

The capacitor plate B is introduced during the personalization process for the particular layer, i.e., the additive or subtractive etching of copper on the laminate.

The deposition of the resistive material A is effe...