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High Density Diode, Transistor Logic Circuit

IP.com Disclosure Number: IPCOM000085462D
Original Publication Date: 1976-Apr-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 2 page(s) / 51K

Publishing Venue

IBM

Related People

Gruodis, AJ: AUTHOR [+2]

Abstract

This semiconductor chip layout requires less silicon area for a diode transistor-logic (DTL) circuit than in previous structures. The layout of a bipolar circuit must be rectangular for optimum circuit density. For the DTL circuit shown in Fig. 1, the component layout shown in Fig. 2 exhibits a very high circuit-to-semiconductor area density.

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High Density Diode, Transistor Logic Circuit

This semiconductor chip layout requires less silicon area for a diode transistor-logic (DTL) circuit than in previous structures. The layout of a bipolar circuit must be rectangular for optimum circuit density. For the DTL circuit shown in Fig. 1, the component layout shown in Fig. 2 exhibits a very high circuit-to- semiconductor area density.

For this layout, the circuits must be interdigitated in pairs with the number of vertical wiring channels determined as a function of circuit count on the chip.

The logic Schottky barrier diodes (SBD) are preferably located in the center of the layout with vertical ground and wiring channels, which can connect to any individual cell. For a specific circuit, the logic SBD's are connected to the circuit input by a second level of metallization, which runs over the first level wiring channels. The SBD's are physically located at the output of the preceding circuit, thereby providing a very efficient design.

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