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Browse Prior Art Database

Low Cost Large Scale Integration Single Chip Module Package

IP.com Disclosure Number: IPCOM000085485D
Original Publication Date: 1976-Apr-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 2 page(s) / 62K

Publishing Venue

IBM

Related People

Jarvela, RA: AUTHOR

Abstract

In this module structure, a semiconductor chip is mounted on an intermediate element provided with a fan-out pattern, and the intermediate element is joined to the module substrate. This structure utilizes the high-density capability of multilayer ceramic technology, by combining it with a low-cost pin carrier capability of the metallized ceramic module.

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Low Cost Large Scale Integration Single Chip Module Package

In this module structure, a semiconductor chip is mounted on an intermediate element provided with a fan-out pattern, and the intermediate element is joined to the module substrate. This structure utilizes the high-density capability of multilayer ceramic technology, by combining it with a low-cost pin carrier capability of the metallized ceramic module.

In this package, an integrated circuit semiconductor device 1 is mounted on a multilayer ceramic space transformer 2 which uses moly lines on the bottom surface 9 and filled vias 5 and 7, to provide fan-out of the inner rows of the chip I/O paths to the outer perimeter of the multi-layer ceramic transformer 2. The outer row of chip I/O pads is joined preferably by solder bonding to surface pads and lines of Cr-Cu-Cr 4.

The space transformer 2 is bonded to the metallized ceramic substrate 3 using a high-temperature resistant epoxy in a cavity 6. The joined substrate assembly of 2 and 3 are then surface-finished as required. The substrate 3 is provided with a metallized pattern 8 of chromium, copper, chromium lines as in the conventional metallized ceramic process, and is etched to provide the top surface lines and bull's-eye pattern.

The metallized lines 8 on the substrate 3 are connected to the inner and outer chip termination leads on transformer 2 and to the respective pins 10 on the substrate. The metallurgy pattern 8 and 4 is formed on the top of the...