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Memory Prefetch

IP.com Disclosure Number: IPCOM000085490D
Original Publication Date: 1976-Apr-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 2 page(s) / 49K

Publishing Venue

IBM

Related People

Aichelmann, FJ: AUTHOR

Abstract

Engine (controller) applications which use very slow response memory storage subsystems/basic storage modules (BSM), essentially require two types of memory information: data and instructions. Data addresses are random and not sequential while instruction addresses are sequential. Therefore, memory transfers of sequential operations (an instructional data path) can be extended or curtailed, depending on the information contents of the selected instruction.

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Memory Prefetch

Engine (controller) applications which use very slow response memory storage subsystems/basic storage modules (BSM), essentially require two types of memory information: data and instructions. Data addresses are random and not sequential while instruction addresses are sequential. Therefore, memory transfers of sequential operations (an instructional data path) can be extended or curtailed, depending on the information contents of the selected instruction.

An instruction-fetch (I-fetch) requesting sequential information is contained in the operand code field of each halfword on the instruction buss. The I-fetch request command from the engine fetches the instruction from the memory array 20, passes the instruction through an error checking control (ECC) 30, if required, and stores the instruction in the I-fetch buffer 40 of the BSM. In this example, the array 20 is either multiplexed or interleaved.

The sequential information is detected by decoding the operand code field and comparing it with branch and jump code points. In this manner, the initial memory transfers can be extended up to the limit of its array interleave, multiplexing, or to a point where a branch or jump condition is detected. A branch or jump condition terminates the sequence, leaving a fully loaded I-fetch buffer.

The engine's instruction processing is now utilized to the maximum because it is not waiting for external (engine) commands, which require additional full memory tran...