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Clocking With Parity and Data Bits

IP.com Disclosure Number: IPCOM000085494D
Original Publication Date: 1976-Apr-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 2 page(s) / 38K

Publishing Venue

IBM

Related People

Aichelmann, FJ: AUTHOR [+2]

Abstract

This is a technique of using data bits and a parity bit to generate a clocking signal for a basic storage module (BSM).

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Clocking With Parity and Data Bits

This is a technique of using data bits and a parity bit to generate a clocking signal for a basic storage module (BSM).

In memory systems the clocking of data from the memory through the logic of the BSM is based upon worst case memory array chip parameters. This results in a fixed or worst case clocking of the external BSM timing, control and interface logic. This technique enables the existence of parity to be used as the clocking signal once the data has been received from the memory component 10.

This is suitable to those applications where an individual memory component 10 satisfies the data width of the BSM to storage interface. This results in the data being available to the user on a response basis, rather than waiting for a fixed clocking internal which is always set for worst case access performance.

The parity associated with this data width could be the same used for ECC (Error Checking and Correction Logic) or simply normal odd parity on those applications not requiring ECC. This technique can be extended to multiple byte components by a logical OR circuit 12, of at least one of the parity (or check bits) and its associated data bits, or all the parity (or check bits) and their associated check bit/bits. The output of OR circuit 12 will indicate that memory data is valid and available as soon as the memory transfer buss from memory component 10 is activated.

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