Browse Prior Art Database

Addressing Mechanism for Engine and Memory Operations

IP.com Disclosure Number: IPCOM000085495D
Original Publication Date: 1976-Apr-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 2 page(s) / 44K

Publishing Venue

IBM

Related People

Aichelmann, FJ: AUTHOR [+2]

Abstract

This is a technique of monitoring the address register in the engine (controller), by the basic storage module (BSM) providing an addressing mechanism for overlapping engine to BSM operations.

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Addressing Mechanism for Engine and Memory Operations

This is a technique of monitoring the address register in the engine (controller), by the basic storage module (BSM) providing an addressing mechanism for overlapping engine to BSM operations.

In engine to BSM applications, the engine operates on one instruction while prefetching the next instruction from the memory. During these operations, the address is being incremented within the engine for the next sequential instruction. As a result, the next address of the memory operation is already known before the engine completes the execution of the instruction it is operating on. Therefore, the address of the next sequential instruction is available before the engine can request this information from the BSM.

The BSM can determine when a memory access is required by monitoring the status line 10 of the engine address register, and comparing this line with the BSM buffer empty line 20. A mismatch will signal that a memory array access is required to satisfy the next engine request. Since an updated address is already on the engine - BSM address buss 30, an early memory array access can be initiated. This produces an overlapping of the next memory request into the current engine operation, resulting in a speedup in response to subsequent engine requests.

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