Browse Prior Art Database

Dynamic Array Return Address Validation

IP.com Disclosure Number: IPCOM000085496D
Original Publication Date: 1976-Apr-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 2 page(s) / 36K

Publishing Venue

IBM

Related People

Aichelmann, FJ: AUTHOR

Abstract

Described are engine/controller applications which require a check of the addressed memory location versus the actual (physical) implemented memory address space. This check is used to insure that the memory address mechanism and operating system programs (i.e., from the engine) are operating consistent with the actual implemented memory arrays.

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Dynamic Array Return Address Validation

Described are engine/controller applications which require a check of the addressed memory location versus the actual (physical) implemented memory address space. This check is used to insure that the memory address mechanism and operating system programs (i.e., from the engine) are operating consistent with the actual implemented memory arrays.

Present basic storage module (BSM) configurations require separate memory array timings and controls to select the specific memory location. This technique combines the memory array selects at the card level with a return line "address valid return buss", to achieve an acknowledgement that the requested range of memory is actually implemented at the BSM. This is as shown in the diagram.

BSM card control logic and timing circuits 10 interfaces between the engine and a plurality of array cards No. 1 through No. N. Address, Select, Timing, and Data Busses connect the circuits 10 with each of the array cards. The address valid return buss connects each of the card select lines back to circuits 10, in order to acknowledge that the requested range of memory is implemented at the BSM.

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