Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

Distributed Address Checking

IP.com Disclosure Number: IPCOM000085497D
Original Publication Date: 1976-Apr-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 2 page(s) / 30K

Publishing Venue

IBM

Related People

Aichelmann, FJ: AUTHOR

Abstract

Described is an engine (Controller) to basic storage module (BSM) application, where address checking (parity) is required on a distributed basis rather than on a transmitted basis. In the BSM this address parity checking of the memory array address can be accomplished on this received basis.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 100% of the total text.

Page 1 of 2

Distributed Address Checking

Described is an engine (Controller) to basic storage module (BSM) application, where address checking (parity) is required on a distributed basis rather than on a transmitted basis. In the BSM this address parity checking of the memory array address can be accomplished on this received basis.

This technique is achieved by computing the appropriate parity at the time the addresses are sent to the memory arrays, but not transmitted. The parity is then saved waiting for a computed parity return from the array card. This returned parity bit/bits then not only includes a check of the parity received from BSM logic, but also includes the path and associated array card circuits. The comparison of the original generated parity against the returned computed parity detects an error condition and provides this distributed address checking. This is shown in the diagram.

1

Page 2 of 2

2

[This page contains 2 pictures or other non-text objects]