Browse Prior Art Database

Level Converting Circuit

IP.com Disclosure Number: IPCOM000085500D
Original Publication Date: 1976-Apr-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 2 page(s) / 29K

Publishing Venue

IBM

Related People

Blaser, EM: AUTHOR [+2]

Abstract

The purpose of the illustrated circuit is to interface bipolar logic levels (0 to 2.4 V) to field-effect transistor (FET) logic levels (0 to 5.0 V). It is used primarily at the input pads of FET chips that must receive bipolar logic levels.

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Level Converting Circuit

The purpose of the illustrated circuit is to interface bipolar logic levels (0 to
2.4 V) to field-effect transistor (FET) logic levels (0 to 5.0 V). It is used primarily at the input pads of FET chips that must receive bipolar logic levels.

Device T1 is a depletion mode N-channel FET and device T2 is an enhancement mode N-channel FET. Devices T1 and T2 form a voltage divider. The width-to-length ratios are selected to produce 3.0 V at node 1. This voltage is used to bias the gate of device T4 (an enhancement mode device). When the input (to the source of T4) is at ground, device T4 turns on and the output is also at ground.

When the input to device T4 is high (approx. 2.4 V), T4 turns off permitting device T3 to change the output node (2) to +5.0 V.

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