Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

Level Converting Circuit

IP.com Disclosure Number: IPCOM000085501D
Original Publication Date: 1976-Apr-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 2 page(s) / 22K

Publishing Venue

IBM

Related People

Askin, HO: AUTHOR [+2]

Abstract

This is a field-effect transistor (FET) circuit for converting bipolar transistor logic levels to FET logic levels.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 100% of the total text.

Page 1 of 2

Level Converting Circuit

This is a field-effect transistor (FET) circuit for converting bipolar transistor logic levels to FET logic levels.

Devices T1 and T2 are depletion mode N-channel FET devices with a threshold voltage of approximately -2.0 Volts. Typically, device T1 has a width- to-length (W/L) ratio of 0.56/0.13, while device T2 has a W/L ratio of 5.0/0.13.

When input 1 (typically from off-chip) is at 0 Volts device T2 is on and the output node 2 is brought to 0 Volts. When input 1 is brought to +2.4 Volts (bipolar logic uplevel), then device T2 is turned off. This permits device T1 to change output node 2 to +5.0 Volts (the FET logic uplevel).

1

Page 2 of 2

2

[This page contains 1 picture or other non-text object]