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Amorphous Bubble Wafer Design for High Yield

IP.com Disclosure Number: IPCOM000085570D
Original Publication Date: 1976-Apr-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 2 page(s) / 41K

Publishing Venue

IBM

Related People

Ahn, KY: AUTHOR [+3]

Abstract

A method is provided for diminishing the occurrence of electrical shorts between the amorphous bubble-supporting material, i.e., GdCoMo, and the pads above it.

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Amorphous Bubble Wafer Design for High Yield

A method is provided for diminishing the occurrence of electrical shorts between the amorphous bubble-supporting material, i.e., GdCoMo, and the pads above it.

As seen in Fig. 1, a typical bubble device would comprise a substrate wafer 2 of silicon, onto which is deposited a layer 4 of GdCoMo, or other bubble- supporting material, over which is deposited an overall insulating SiO(2) layer 6. Electrical circuitry, in the form of chip regions 8, are deposited, through conventional lithographical techniques, onto the GdCoMo. Lead lines 10, for actuating the circuitry, emanate from pads 12, the latter being relatively large conductive regions for receiving signals from a source of electrical power, not shown.

If such pads are located so that there is GdCoMo lying below the SiO(2) and beneath the pad 12, there is an increased probability that electrical shorts will take place between a pad 12 and the GdCoMo. To avoid or considerably diminish such shorts, a ring of GdCoMo is removed from the deposited layer 4 (see Fig. 2), so that when SiO(2) is deposited, followed by pad deposition, there is no GdCoMo directly beneath a pad 12.

Such removal of GdCoMo improves the reliability of the completed bubble device, in that it lowers the chances of shorts at the very regions where the highest electric fields occur.

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