Browse Prior Art Database

Raised Junction MOSFET With Low Sheet Resistance Junctions

IP.com Disclosure Number: IPCOM000085571D
Original Publication Date: 1976-Apr-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 3 page(s) / 64K

Publishing Venue

IBM

Related People

Rideout, VL: AUTHOR

Abstract

In a previous publication (Ref. 1), a method for fabricating raised junction metal-oxide semiconductor field-effect transistors (MOSFETs) was described that used ne+ epi layers or implanted regions to provide n+ junctions and interconnection lines. In that process the field isolation oxide was formed after junction fabrication. In addition, the junction depths were kept shallow as would be used in an integrated circuit memory process where low n+ sheet resistance is not a major requirement.

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Raised Junction MOSFET With Low Sheet Resistance Junctions

In a previous publication (Ref. 1), a method for fabricating raised junction metal-oxide semiconductor field-effect transistors (MOSFETs) was described that used ne+ epi layers or implanted regions to provide n+ junctions and interconnection lines. In that process the field isolation oxide was formed after junction fabrication. In addition, the junction depths were kept shallow as would be used in an integrated circuit memory process where low n+ sheet resistance is not a major requirement.

In the present method a different approach is described which uses low-sheet resistance polysilicon n+ regions for sources, drains, and interconnection lines. The thick field isolation oxide is formed before depositing the polysilicon regions, and thus the polysilicon can run onto and even across the field isolation oxide. In contrast, in conventional processes the edge of the field oxide is used to define the boundary of the n+ regions. For logic applications, n+ polysilicon interconnection lines with low-sheet resistance would be attractive.

Figs. 1A, 1B, 1C, and 1D illustrate the new technique. First the field isolation regions (e.g., semi- or fully-recessed oxide regions) are fabricated as shown in Fig. 1A. Next the polysilicon layer is deposited and is doped n+ by diffusion or ion implantation of As or P, as shown in Fig. 1B.

Depending upon the deposition conditions, the polysilicon may be single crystalline over the exposed Si areas. This is preferred because then an anisotropic etchant may be used to define the gate region, without undercutting the oxide mask used to pattern the polysilicon regions. Then the gate oxide is grown (500 to 700 Angstrom degrees thick). The oxide grows faster on the sidewalls of the n+ silicon and n+ poly...