Browse Prior Art Database

Double Layer Gate Electrode FET Structure

IP.com Disclosure Number: IPCOM000085572D
Original Publication Date: 1976-Apr-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 2 page(s) / 39K

Publishing Venue

IBM

Related People

Bassous, E: AUTHOR [+3]

Abstract

A method is described for improving the reliability of a field-effect transistor (FET) gate structure by utilizing a double layer of Al and polycrystalline silicon metallurgy.

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Double Layer Gate Electrode FET Structure

A method is described for improving the reliability of a field-effect transistor (FET) gate structure by utilizing a double layer of Al and polycrystalline silicon metallurgy.

A p-type silicon body 1 having a thin SiO(2) layer 2 is shown in step 1. A poly-Si layer 3 is deposited by a chemical vapor deposition (CVD) process (or any other compatible process, such as evaporation or sputtering, etc.) as shown in step 2. The poly-Si layer 3 can be doped during deposition or by diffusion after the deposition. An etch mask layer such as SiO(2), not shown, may be used on top of the poly-Si layer 3, as shown in step 3, so that contact holes 4 can be delineated through the poly-Si layer. Al metal 5 is then deposited and delineated (step 4). The poly-Si layer 3 is then etched, as shown in step 5.

Pd(2)Si or PtSi contact metallurgy can be used if required to further reduce contact resistance. Such a contact metallurgy can be applied after the contact holes are etched and before Al is deposited. Source, gate and drain contacts are prepared in a conventional manner.

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