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Josephson Feedback Memory Cells

IP.com Disclosure Number: IPCOM000085576D
Original Publication Date: 1976-Apr-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 4 page(s) / 51K

Publishing Venue

IBM

Related People

Henkels, WH: AUTHOR

Abstract

A Josephson junction memory cell which incorporates magnetic feedback into a selected cell, in order to produce an effective asymmetry which allows a mode of operation not requiring a special initiating cycle is described. The resulting cell has advantages over a cell proposed by Anacker and Zappe [1,4], including a capacity for increased inherent operating margins and very flexible design. Magnetic feedback in single Josephson gates has been discussed by Zappe [2], who showed that the effective gain of a Josephson gate could be increased by using the gate supply line as one of the gate controls. In the memory cell array discussed below, which incorporates gates having feedback, it is not the increased gate gains that is primarily utilized, but rather the resulting asymmetry in the switching threshold curves.

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Josephson Feedback Memory Cells

A Josephson junction memory cell which incorporates magnetic feedback into a selected cell, in order to produce an effective asymmetry which allows a mode of operation not requiring a special initiating cycle is described. The resulting cell has advantages over a cell proposed by Anacker and Zappe [1,4], including a capacity for increased inherent operating margins and very flexible design. Magnetic feedback in single Josephson gates has been discussed by Zappe [2], who showed that the effective gain of a Josephson gate could be increased by using the gate supply line as one of the gate controls. In the memory cell array discussed below, which incorporates gates having feedback, it is not the increased gate gains that is primarily utilized, but rather the resulting asymmetry in the switching threshold curves.

Fig. 1 shows a schematic of a portion of an array 1 of memory cells 2 incorporating magnetic feedback into the write gates 3. Write gates 3 have two controls, the word current, 1(w), and the bit current, I(B).

The total control current, I(c), for a selected cell A is I(c) = I(w) + I(B). Assuming that cells 2 have equal branch inductances, I(g) = C + (I(w)/2) where C is the cell circulating current due to the previous history of the cell. Fig. 2a displays the selected cell operating points for a standard write cycle, in this instance changing the stored circulating current from C = +I(w)/2 to C = -I(w)/2. The solid line depicts the write gate switching threshold curve. Fig. 2b displays the corresponding word and bit current timing, and the resultant write gate supply current.

At time t(o), the only contribution to I(g) is the circulating current C = 0.5 (operating point a). Application of the word current of amplitude 1 unit results in an increase in I(g) of I(w)/2 = 0.5 unit along with a control current of 1 unit (I(c) = I(b) + I(w) = 0 1), resulting in a shift in the operating point to b. Application of the bit current causes switching of the write gate during transit to point c.

After the write gate switches, all of the current in the write gate branch transfers to the opposite branch, hence point d is reached (assuming for simplicity that I(min) = 0). Removal of bit current shifts the operating point to e. Finally, removal of word current (1 unit) removes 1 unit of control and 0.5 unit of gate current, resulting in point f where C = -0.5.

The bottom waveform of Fig. 2b shows the write gate supply current for the case in which the same cycle is applied to a cell already possessing C = -0.5; as can be seen, no change in C results. Writing the opposite sense requires reversal of word and bit polarities.

During a write cycle, the control current for the selected cell (cell A of Fig. 1) is I(B) + I(w), whereas the control current for an unselected cell (B in Fig. 1) along the bit direction is simply I(B).

When plotted in the I(g) - I(B) plane, the switching threshold curves for A and B display th...