Browse Prior Art Database

Wide Margin Nonlatching Josephson Logic Family

IP.com Disclosure Number: IPCOM000085589D
Original Publication Date: 1976-Apr-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 3 page(s) / 48K

Publishing Venue

IBM

Related People

Landman, BS: AUTHOR [+2]

Abstract

The use of three junction interferometers as low-current, high-gain logic devices is known. In addition, the use of such interferometers as nonlatching logic circuits by simply connecting a low impedance terminated transmission line across the device has been suggested. The mode of operation is the same as that of the Josephson amplifier (U.S. Patent 3,913,027 entitled "High Gain, Large Bandwidth Amplifier Based on the Josephson Effect", H. H. Zappe, assigned to IBM), except that the hysteresis of the total device is not entirely suppressed but remains small.

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Wide Margin Nonlatching Josephson Logic Family

The use of three junction interferometers as low-current, high-gain logic devices is known. In addition, the use of such interferometers as nonlatching logic circuits by simply connecting a low impedance terminated transmission line across the device has been suggested. The mode of operation is the same as that of the Josephson amplifier (U.S. Patent 3,913,027 entitled "High Gain, Large Bandwidth Amplifier Based on the Josephson Effect", H. H. Zappe, assigned to IBM), except that the hysteresis of the total device is not entirely suppressed but remains small.

Such a device will switch from the zero voltage state into the voltage state when a control is applied. While in the voltage state almost the entire gate current is transferred into the transmission line. Upon removal of the control the device reverts back into the zero voltage state, without requiring a reset through a pulsed gate current or a reset by any other means. Thus, DC powering is possible.

The margins of nonlatching interferometers are larger than those of other Josephson logic circuits. It is the purpose of this description to show how still considerably larger margins can be obtained by using not a single, but several such circuits to build a family of nonlatching AND, NOR, and INVERT circuits.

The basic nonlatching interferometer circuit is shown in Fig. 1. It is a terminated line logic circuit except that the terminating resistor R(T) is chosen such that the damping parameter Beta has a value of < 2, where: Beta = 2 Pi C R(T)/2/I(m) over Phi(o) with C being the total junction capacitance, I(m) the total Josephson threshold current and Phi(o), the magnetic flux quantum.

The I-V characteristic of the total device is shown in Fig. 2. Plotting the current through the device versus the voltage across the output control line, it is seen that only a small amount of hysteresis is left. By proper adjustment of the gate current the device of Fig. 1 is in the zero voltage state in absence of control current, and in the voltage state if the control current is applied.

The circuit of Fig. 3 contains several devices 1 such as shown in Fig. 1. Each device 1 has only two control lines, one bias line 2 and one input line 3. The fan-in is increased by connecting devices 1 in parallel as shown...