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# Josephson Logic Circuits With Nonlinear Addition of Inputs

IP.com Disclosure Number: IPCOM000085590D
Original Publication Date: 1976-Apr-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 4 page(s) / 64K

IBM

## Related People

Herrell, DJ: AUTHOR [+2]

## Abstract

The AND gate shown in Fig. 1 has relatively poor operating margins when compared to the OR gate shown in Fig. 2. The minimum "1" output level of the OR gate, i(1), is given by:. (Image Omitted) with the usual notation for maximum and minimum limits (e.g., A and A, respectively), and where I1 corresponds to the parallel combination.

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Josephson Logic Circuits With Nonlinear Addition of Inputs

The AND gate shown in Fig. 1 has relatively poor operating margins when compared to the OR gate shown in Fig. 2. The minimum "1" output level of the OR gate, i(1), is given by:.

(Image Omitted)

with the usual notation for maximum and minimum limits (e.g., A and A, respectively), and where I1 corresponds to the parallel combination.

Typically R(L) = 0.1 R(s) and R(s) = R(j) and hence i(-1) = 1 over 1.2 {V(- s)/R(s)}. (2).

For the AND gate, the minimum output 1 level, i(-2), is given approximately by:

(Image Omitted)

since there are effectively three junctions in parallel in the 1 state for the AND gate. (It should be noted that in Fig. 1 r << R(j).) Thus, with the same numerical values used for expression (2):

(Image Omitted)

is obtained.

The AND gate shown herein in Fig. 3 essentially restores the minimum output current level (i(3)) of the AND gate to the same level as that anticipated from the OR gate. Referring to Fig. 3, the minimum output 1 level, i(-3), is given approximately by:

(Image Omitted)

Once again substituting typical values;

(Image Omitted)

is obtained, since r is negligible compared with R(s) and R(j) [.03]. It should be noted that the overall dissipation of this AND gate remains essentially the same (slightly reduced) as that of the original design. The switching delay of the gate can be considered as being increased by a further "cascade" delay (estimated at approximately 10 pS].

An alte...