Browse Prior Art Database

Signal Transition Detector

IP.com Disclosure Number: IPCOM000085593D
Original Publication Date: 1976-May-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 2 page(s) / 31K

Publishing Venue

IBM

Related People

Grimes, DW: AUTHOR

Abstract

The circuit as diagrammed is simple and inexpensive, but permits higher density packaging than previous circuits due to its smaller size. The circuit provides a negative output pulse of uniform width for each positive transition or alternatively, a similar positive pulse for each negative transition of an input signal.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 55% of the total text.

Page 1 of 2

Signal Transition Detector

The circuit as diagrammed is simple and inexpensive, but permits higher density packaging than previous circuits due to its smaller size. The circuit provides a negative output pulse of uniform width for each positive transition or alternatively, a similar positive pulse for each negative transition of an input signal.

The basic part of the circuit is a vendor's module having a P channel field-effect transistor (FET) 1 and an N channel FET 2 in series thereon between the positive 3 and ground 4 voltage terminals. The substrate terminals 5 and 6 of the respective FET's 1 and 2, indicated as gates on the drawing, are connected to the voltage terminals 3 and 4, respectively.

The common node 7, the drains of the FETs, is connected to an output terminal 8 and to one end of a resistor 9. The other end of resistor 9 may be connected to either terminal 3 or terminal 4 by a jumper 10, to enable the circuit to respond to positive or negative input transitions.

A capacitor 11 and a resistor 12 are connected between the input terminal 20 and voltage terminal 3, with their common point connected to the gate 13 of FET
1. A second capacitor 14 and second resistor 15 are connected between input terminal 20 and the ground terminal 4, with their junction connected to gate 16 of FET 2.

In operation with jumper 10 in the position indicated, the output 8 is floating at positive 3 level due to resistor 9 being a pull-up resistor When a positive transition oc...