Browse Prior Art Database

Complimentary FET Memory Cell

IP.com Disclosure Number: IPCOM000085613D
Original Publication Date: 1976-May-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 2 page(s) / 60K

Publishing Venue

IBM

Related People

Garnache, RR: AUTHOR

Abstract

Described herein is the structure of a four-device complimentary field-effect transistor (FET) bistable circuit in three dimensions. The structure consists of N channel FET devices fabricated in a P type substrate and P channel FET's fabricated in overlaying polycrystalline silicon. By having the drains of the N channel devices act as the gates of the P channel devices and vice versa, it is possible to lay out the circuit in extremely compact form.

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Complimentary FET Memory Cell

Described herein is the structure of a four-device complimentary field-effect transistor (FET) bistable circuit in three dimensions. The structure consists of N channel FET devices fabricated in a P type substrate and P channel FET's fabricated in overlaying polycrystalline silicon. By having the drains of the N channel devices act as the gates of the P channel devices and vice versa, it is possible to lay out the circuit in extremely compact form.

Fig. 1 is a circuit diagram showing FET devices 1, 2, 3, and 4 and the address transistor 5. The FET devices 1 and 3 are also shown in cross section in Fig. 4, while devices 2 and 4 are further illustrated in cross section in Figs. 5 and 6. Fig. 2 illustrates a top view lay out with P+ polycrystalline silicon at 6 and
7. N polysilicon at 8 with N diffusions at 8, 9, 10, and 11. An aluminum word line is shown at 12. Device gates are labeled G1, G2, G3, G4, and G5.

Fig. 3 is a section through 3-3 of Fig. 2 showing the word line structure with ground line diffusion 9. Drain 10 shown, in bit line 11, and a thin oxide layer 14, the aluminum word line 12, which forms the address transistor 5 overlaying the polysilicon and oxide as shown at 6 and 15, and field oxide thick insulator 13.

The devices 1 and 3 of Fig. 1, shown in Fig. 4, show thick oxide insulator 13 with thin oxide insulator 14, and a N- polysilicon overlay containing diffusion 11 and remaining N+ diffusions are also illustrated. Pol...