Browse Prior Art Database

Planar Semiconductor Storage Array

IP.com Disclosure Number: IPCOM000085614D
Original Publication Date: 1976-May-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 2 page(s) / 66K

Publishing Venue

IBM

Related People

Bhattacharyya, A: AUTHOR [+3]

Abstract

A substantially planar topography enhances the photo-yield of a semiconductor storage array.

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Planar Semiconductor Storage Array

A substantially planar topography enhances the photo-yield of a semiconductor storage array.

Parallel and spaced apart isolation strips 10, such as recessed oxide, are provided at the surface of a semiconductor substrate 12, as indicated in Fig. 1A, and thin layers of silicon dioxide 14 and silicon nitride 16 are produced over the surface of the substrate 12, as indicated more clearly in Fig. 1B which is a section taken through Fig. 1A at 1B-1B.

Over the silicon nitride 16 and orthogonal to the isolation strips 10 is formed a first plurality of strips of polysilicon P1, by employing a masking material such as aluminum 18 which is suitably etched along with the polysilicon P1. N/+/ diffusion regions 20 and 20' are then formed by ion implantation through layers 14 and 16.

By using a block mask, strips of photoresist 22 are formed over diffusion regions 20', which is followed by vacuum deposition of a second plurality of strips of polysilicon P2 indicated in Figs. 2A and 2B. The strips P2 over the aluminum 18 and the photoresist 22 are removed by employing any suitable lift-off process. The strips P1 and the remaining strips P2 are thermally oxidized to form insulating layers 24, contacts over diffusions 20' are opened and a conductive line 26, which may be made of aluminum, interconnects the diffusion regions 20', as shown in Figs. 3A and 3B.

As can be seen more clearly in Figs. 3A and 3B, the storage array is formed of one-device...