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Recessed Gate One Device Cell Memory Array

IP.com Disclosure Number: IPCOM000085615D
Original Publication Date: 1976-May-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 2 page(s) / 83K

Publishing Venue

IBM

Related People

Landler, PF: AUTHOR [+2]

Abstract

A one-device cell for a semiconductor memory array utilizes a transistor having a gate electrode disposed within a recess in the semiconductor substrate.

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Recessed Gate One Device Cell Memory Array

A one-device cell for a semiconductor memory array utilizes a transistor having a gate electrode disposed within a recess in the semiconductor substrate.

As indicated in Fig. 1A and in Fig. 1B, which is a section taken through Fig. 1A at 1B-1B, a recessed oxide grid 10 is formed in a semiconductor substrate 12 around the areas protected by the layers of silicon nitride 14A and 14B and pyro- oxide 16. In regions 10A and 10B where gate electrodes are to be formed, the recessed oxide grid 10 is etched while the remaining portions of the grid 10 are protected by a layer of photoresist 18, as indicated in Figs. 2A and 2B.

A thin gate oxide layer 20 is formed before depositing a first polysilicon layer 22, which is doped and etched and then oxidized to form insulating layer 24, as shown in Figs. 3A and 3B. Silicon nitride layer 14B is removed by employing a suitable masking operation. A thin layer of oxide under layer 14B is also removed and an appropriate thickness of silicon dioxide 26 is regrown for the dielectric of the storage capacitor of the cells.

A second layer of polysilicon 28 is deposited over the silicon dioxide layer 26, suitably doped and oxidized to form insulating layer 30, as illustrated in Figs. 4A and 4B. Silicon nitride layer 14A is then dip etched along with the oxide pad beneath layer 14A.

A heavily doped region 32 is formed by either diffusion or ion implantation and drive-in is provided without reoxidation. Appropriate contacts...