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Browse Prior Art Database

High Speed FET Decoder

IP.com Disclosure Number: IPCOM000085617D
Original Publication Date: 1976-May-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 2 page(s) / 35K

Publishing Venue

IBM

Related People

Parikh, GH: AUTHOR

Abstract

This field-effect transistor (FET) decoder circuit allows improved speed of decoding FET random-access memories, by reducing the capacitance required to be discharged in an unselected decoder.

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High Speed FET Decoder

This field-effect transistor (FET) decoder circuit allows improved speed of decoding FET random-access memories, by reducing the capacitance required to be discharged in an unselected decoder.

In a memory array in which 1 of 2N word lines is to be selected during an access cycle, NOR circuits are typically used because of the speed advantage obtained in discharging 2N-1 precharged voltage nodes, as opposed to charging a single gating node for selection of a word line. In this circuit the speed is further increased by reducing the capacitance of the nodes to be discharged.

In the circuit shown a NOR circuit comprising precharging device T1 and selection devices T2 is provided for decoding 2N-1 of the storage address register inputs, SAR1 to SAR(N-1). Word line drive pulse VW is decoded to 1 of 2 inputs by the SARN input signal by VW1 and VW2 generations 10 and 12 plus T7 and T8. One of the bootstrapped drivers T5 or T6 will allow word Line A or B to be driven for selection. Isolation devices T3 and T4 are provided to isolate the capacitance on nodes N2 and N3 to allow bootstrapping to occur if node N1 has not been discharged.

Conventionally, the gates of T3 and T4 are biased at a DC isolation potential
IV. In this circuit two IV Generators 14 and 16 are provided which are additionally decoded by the SARN input signal applied to T9 and T10.

In a typical circuit, parasitic capacitance C2 and C3 are fairly large and nodes N2 and N3 must be disc...