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User Configurable Local Storage Registers

IP.com Disclosure Number: IPCOM000085625D
Original Publication Date: 1976-May-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 5 page(s) / 41K

Publishing Venue

IBM

Related People

Albert, AJ: AUTHOR

Abstract

A mechanism is described for use with a data processor wherein different types of registers such as general-purpose registers, index registers, floating-point registers and the like are located in a local storage array. The mechanism enables the programmer or user to customize or configure the register space in local storage, so as to provide the optimum arrangement of registers in terms of numbers and types to best suit his particular application.

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User Configurable Local Storage Registers

A mechanism is described for use with a data processor wherein different types of registers such as general-purpose registers, index registers, floating- point registers and the like are located in a local storage array. The mechanism enables the programmer or user to customize or configure the register space in local storage, so as to provide the optimum arrangement of registers in terms of numbers and types to best suit his particular application.

In processors currently on the market in which user addressable registers are implemented in local storage, optimum utilization of the local storage resource is not always completely possible in those cases where more than one type of user addressable register exists in the architecture. This is because the partitioning of the local storage array into sets of registers of particular types may not be appropriate for the application to be processed. For example, a processor may have special registers for floating-point arithmetic whose array space could be far better utilized as additional index registers by an application which performs no floating-point operations.

In order to explain the basic concepts of the technique described herein, a local storage array having the dimensions shown in the drawing will be used by way of example to explain one possible implementation of the new technique. This array has 64 addressable locations and each location has a width of 128 bits. Addressing any given location will cause a parallel readout of all 128 bits at such location by way of a 128-conductor array output data bus. For convenience, the 128 bits at each location are called a full array word. The registers being considered herein are to be located in the high-address half (locations 32-63) of the local storage array.

For sake of example, it is assumed that the following five types of registers can be located in the register space of the local storage array: 32-bit index registers.

64-bit binary/logical accumulators.

64-bit hexadecimal floating-point registers.

128-bit decimal floating-point registers.

128-bit addressing registers.

Taking 128 bits as being a full array word, the 32-bit registers will be called quarterword registers, the 64-bit registers will be called halfword registers and the 128-bit registers will be called fullword registers. Four typical quarterword registers are indicated at A, B, C and D in the drawing. Two typical halfword registers are indicated at E and F and a typical fullword register is indicated at G. The choice of the number of each type and of their location in the register space is under the control of the programmer, except that the proper boundary alignment conditions must be observed. In other words, any given halfword register must be either left aligned (position E) or right aligned (position F).

In a similar vein, any given quarterword register must be aligned in one of the quarterword positions represented by...