Browse Prior Art Database

High Speed Programmable Buffer

IP.com Disclosure Number: IPCOM000085638D
Original Publication Date: 1976-May-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 4 page(s) / 60K

Publishing Venue

IBM

Related People

Kosky, FG: AUTHOR [+4]

Abstract

Described is the architecture for a high-speed programmable buffer capable of outputting large data words synchronously at its channel interface. It also provides, because of its programmability, a large decrease in the data input requirement normally needed to support redundant data patterns, while not disturbing the specified continuous synchronous data output.

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High Speed Programmable Buffer

Described is the architecture for a high-speed programmable buffer capable of outputting large data words synchronously at its channel interface. It also provides, because of its programmability, a large decrease in the data input requirement normally needed to support redundant data patterns, while not disturbing the specified continuous synchronous data output.

The high-speed programmable buffer (HSPB) is comprised of two main sections:
A. An asynchronous miniprocessor section capable of fetching and

executing sequentially, customized op code command instructions.
B. A synchronous large word data buffer (data operand) section.

The major difference in the HSPB miniprocessor from conventional processors or computers, is in the meaning as well as the operation of the HSPB instruction word format shown at 1.

In conventional computers, the instruction is made up of op codes and operands where the operands are purposely constructed to contain the address of where the data lies for the intended operation prescribed by the instructions op code. In the HSPB this is not so; here operands are referred to as immediate or work operands. They are referred to as work operands because they contain all the given data necessary to perform the designated command of the op code. Because of this and since the processor execution is asynchronous or performed via sequential logic, instruction cycles (I-cycle) are not needed with one exception which is simply the instruction fetch itself. Hence, much speed is gained since there is no need to locate and move the data to a work area.

Although the figure shows two work operands, the number can be larger, or each operand could have subset operands or partitions as long as it will provide enough information to execute the op code command, and as long as the partitions do not break over any of the full bit boundaries originally assigned to the basic operand. The data operand field will contain the data word which will be outputted at a specified synchronous speed. It will be data requiring no modification.

The only time it is required to write into the memory 2 is when the memory is to be loaded from some outside input device, or a computer working at a slower repetition rate. The operation of the HSPB can be described in four basic steps. Starting with any instruction address anywhere from n to r, as indicated on the figure, the following is provided:

1. The instruction address is applied via the memory address register (MAR) 3 along with the proper timing pulse, select, and the read line supplied by the memory address, timing and gate controlled logic 4.

2. After the memory access time has elapsed, the total instruction will be set into the MDR (memory data register) latches 5.

1

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3. At this point, the op code is applied to decoder 6 and its decoded gate signal is transmitted to both the execution logic and the memory address, timing, and gate controlled logic 4.

4...