Browse Prior Art Database

In Line Wafer Quality Monitor

IP.com Disclosure Number: IPCOM000085649D
Original Publication Date: 1976-May-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 2 page(s) / 35K

Publishing Venue

IBM

Related People

Edmonds, HD: AUTHOR [+2]

Abstract

The cathodic current technique is coupled to a light-emitting diode (LED) scanning system to produce semiconductor product wafer quality maps which separately identify substrate, diffusion and epi problems.

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In Line Wafer Quality Monitor

The cathodic current technique is coupled to a light-emitting diode (LED) scanning system to produce semiconductor product wafer quality maps which separately identify substrate, diffusion and epi problems.

The test device is illustrated in the figure and consists of vacuum chuck 1 of an insulative material which holds, seals off, and makes electrical contact to the backside of wafer 2. Arm 3, carrying a vacuum line and electrical line, inserts wafer 2 into an electrolyte solution 4, such as dilute sulfuric acid, in cell 5. Array 6 of LED's or other suitable light sources, which are capable of selectively illuminating small segments of the wafer surface, is arranged opposite to the surface of the wafer 2. Scanning electronics 7 and meter 8 are provided to measure cathodic current information on different segments of the wafer. This information is processed by computer 9.

The tests are conducted at various processing stages during device manufacture, so that low-quality wafers can be removed prior to additional costly processing. For example, the initial P type wafers are tested before processing, after N/+/ collector diffusion, and after N/-/ epi layer growth by negatively biasing the wafer 2, and determining current shifts at different segments of the wafer which are induced by the light. The testing detects problems due to both incoming wafer quality and process steps. The information gathered at each stage permits a timely decisio...