Browse Prior Art Database

Memory Controller Sequential Instruction (I) Fetch Operation

IP.com Disclosure Number: IPCOM000085659D
Original Publication Date: 1976-May-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 2 page(s) / 57K

Publishing Venue

IBM

Related People

Aichelmann, FJ: AUTHOR [+2]

Abstract

The memory/controller (engine) sequential instruction (I) fetch operation provides a fast instruction path for a series of sequential instructions and increases the addressability of the memory, by extending the memory data transfer beyond its physical interface.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 83% of the total text.

Page 1 of 2

Memory Controller Sequential Instruction (I) Fetch Operation

The memory/controller (engine) sequential instruction (I) fetch operation provides a fast instruction path for a series of sequential instructions and increases the addressability of the memory, by extending the memory data transfer beyond its physical interface.

The action is based upon the sequential requirements of the instructions required for the engine. The initial memory reference provides the extended transfer. Extended transfers are accomplished, because the memory array is organized around a multiple bit large-scale integration (LSI) chip. Every bit on an LSI chip is selected but only one is normally supplied for memory transfers, because of error checking and control (ECC) requirements on the memory storage subsystem at the array card level.

During engine data flow, the remaining bits are also transferred from the memory arrays. The basic of the request is the internal control structure in the engine and is signalled from branches. jumps and program status word (PSW) swaps. Those events signal that sequential instruction fetch operations are coming, by decoding the engines instruction register in conjunction with read-only storage (ROS) branch field logic. During load or store operations, the contents of this instruction address register is not changed, therefore maintaining the integrity of the sequential instruction.

A normal memory transfer does not supply the extended data transfer, since...