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Synchronization of Two Controllers Operating in a Duplex Mode

IP.com Disclosure Number: IPCOM000085662D
Original Publication Date: 1976-May-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 2 page(s) / 51K

Publishing Venue

IBM

Related People

DiPilato, NM: AUTHOR

Abstract

The synchronization of two controllers operating in a duplex mode for high reliability, is maintained by a logical comparison, external to the controllers, of all critical control lines. The controllers may operate with their own internal clocks, and their external interfaces may operate asynchronously. Both controllers, one in an active mode and one in a standby mode, operate on the same instruction. A failure in the active controller does not prohibit the standby controller to become the active controller, and continue processing instructions uninterrupted.

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Synchronization of Two Controllers Operating in a Duplex Mode

The synchronization of two controllers operating in a duplex mode for high reliability, is maintained by a logical comparison, external to the controllers, of all critical control lines. The controllers may operate with their own internal clocks, and their external interfaces may operate asynchronously. Both controllers, one in an active mode and one in a standby mode, operate on the same instruction. A failure in the active controller does not prohibit the standby controller to become the active controller, and continue processing instructions uninterrupted.

The figure illustrates the basic connections for two controllers operating in a duplex mode. The I/O interface and memory interface of both controllers operate asynchronously.

For the controller to memory interface, read or write commands are sent to memory and the controller clocks are stopped waiting for a memory data valid response. The data valid from memory blocks A and B are sent to the synchronization compare logic, and a common memory data valid is sent to both controllers.

For the controller to I/O adapter interface, the I/O commands are sent to the synchronization compare logic, and common I/O commands are sent to the I/O adapters. The controller clocks are stopped waiting for a common I/O valid response from the adapter.

As illustrated, both controller clocks are driven by one oscillator. Since both controller clocks are always restarte...